On Tue, Sep 22, 2015 at 06:59:48PM +0100, Robert Richter wrote: > From: Tirumalesh Chalamarla <tchalama...@cavium.com> > > Increase the standard cacheline size to avoid having locks in the same > cacheline. > > Cavium's ThunderX core implements cache lines of 128 byte size. With > current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could > share the same cache line leading a performance degradation. > Increasing the size fixes that.
Do you have an example of that happening? > Increasing the size has no negative impact to cache invalidation on > systems with a smaller cache line. There is an impact on memory usage, > but that's not too important for arm64 use cases. Do you have any before/after numbers to show the impact of this change on other supported SoCs? Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/