Added addtional bindings required for FPGA Manager operation
of the Xilinx Zynq Devc configuration interface.

Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
 arch/arm/boot/dts/zynq-7000.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index dc0457e..1a5220e 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -294,6 +294,11 @@
                devcfg: devcfg@f8007000 {
                        compatible = "xlnx,zynq-devcfg-1.0";
                        reg = <0xf8007000 0x100>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 8 4>;
+                       clocks = <&clkc 12>;
+                       clock-names = "ref_clk";
+                       syscon = <&slcr>;
                };
 
                global_timer: timer@f8f00200 {
-- 
2.6.1

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