[PATCH v2 21/24] kselftest/arm64: add HWCAP test for FEAT_S1POE

[Joey Gouly]

Check that when POE is enabled, the POR_EL0 register is accessible.

Signed-off-by: Joey Gouly <joey.go...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <w...@kernel.org>
Cc: Mark Brown <broo...@kernel.org>
Cc: Shuah Khan <sh...@kernel.org>
---
 tools/testing/selftests/arm64/abi/hwcap.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tools/testing/selftests/arm64/abi/hwcap.c 
b/tools/testing/selftests/arm64/abi/hwcap.c
index e3d262831d91..64bb49fe3f5c 100644
--- a/tools/testing/selftests/arm64/abi/hwcap.c
+++ b/tools/testing/selftests/arm64/abi/hwcap.c
@@ -101,6 +101,12 @@ static void pmull_sigill(void)
        asm volatile(".inst 0x0ee0e000" : : : );
 }
 
+static void poe_sigill(void)
+{
+       /* mrs x0, POR_EL0 */
+       asm volatile("mrs x0, S3_3_C10_C2_4" : : : "x0");
+}
+
 static void rng_sigill(void)
 {
        asm volatile("mrs x0, S3_3_C2_C4_0" : : : "x0");
@@ -379,6 +385,13 @@ static const struct hwcap_data {
                .cpuinfo = "pmull",
                .sigill_fn = pmull_sigill,
        },
+       {
+               .name = "POE",
+               .at_hwcap = AT_HWCAP2,
+               .hwcap_bit = HWCAP2_POE,
+               .cpuinfo = "poe",
+               .sigill_fn = poe_sigill,
+       },
        {
                .name = "RNG",
                .at_hwcap = AT_HWCAP2,
-- 
2.25.1