On Thu, Jun 20, 2024 at 7:57 AM Charlie Jenkins <char...@rivosinc.com> wrote:
>
> The D1/D1s SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Charlie Jenkins <char...@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.doo...@microchip.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
If the RISC-V maintainers want to take the whole series.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 64c3c2e6cbe0..6367112e614a 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -27,7 +27,8 @@ cpu0: cpu@0 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm",
> "xtheadvector";
> + thead,vlenb = <128>;
> #cooling-cells = <2>;
>
> cpu0_intc: interrupt-controller {
>
> --
> 2.34.1
>
