On Fri, Aug 07, 2009 at 10:11:40PM +0200, Laurent Pinchart wrote:
> Ok. Maybe the kernel mapping from L_PTE_MT_UNCACHED to strongly ordered for 
> ARMv6 and up (not sure about how it worked for previous versions) brought 
> some 
> confusion. I'll try to be more precise now.

It's something we should correct.

> Does that mean that, in theory, all DMA transfers in the DMA_FROM_DEVICE 
> direction are currently broken on ARMv7 ?

Technically, yes.  I haven't had a stream of bug reports which tends
to suggest that either the speculation isn't that aggressive in current
silicon, or we're just lucky so far.

> The ARM Architecture Reference Manual (ARM DDI 0100I) states that

Bear in mind that DDI0100 is out of date now.  There's a different
document number for it (I forget what it is.)

> "• If the same memory locations are marked as having different memory types 
> (Normal, Device, or Strongly Ordered), for example by the use of synonyms in 
> a 
> virtual to physical address mapping, UNPREDICTABLE behavior results.
> 
> • If the same memory locations are marked as having different cacheable 
> attributes, for example by the use of synonyms in a virtual to physical 
> address mapping, UNPREDICTABLE behavior results."

Both of these we end up doing.  The current position is "yes, umm, we're
not sure what we can do about that"... which also happens to be mine as
well.  Currently, my best solution is to go for minimal lowmem and
maximal highmem - so _everything_ gets mapped in on an as required
basis.

> This would be broken if a fully cached Normal mapping already existed for 
> those physical pages. You seem to imply that's the case, but I'm not sure to 
> understand why.

The kernel direct mapping maps all system (low) memory with normal
memory cacheable attributes.

So using vmalloc, dma_alloc_coherent, using pages in userspace all
create duplicate mappings of pages.
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