Hi Sylwester Nawrocki,

I have some suggestion about s5p-fimc camera driver.
As you know, FIMC have 32 ping-pong register(CIOYSA1~CIOYSA32) for output 
buffer in v310 chip. It is different from v210.
It is not necessary to change address at ping-pong register.
If request buffer number is 8, 8 buffer can be set at ping-pong register.

- active_buf_q / pending_buf_q 

The list_head pending_buf_q is not necessary for v310. Because, it is possible 
to set output buffer until 32. 
There is no case that request buffer number is over 32.
So, I think pending_buf_q is not use in v310. Instead, it can be used 
active_buf_q. 
Of course, The use of active_buf_q may be different from the present. 

For intstance, ISR may be changed follow.

a. Read FrameCnt_before(CISTATUS2) - This is for what is written buffer(index) 
just.
b. Disable a proper bit of FrameCnt_Seq(CIFCNTSEQ) and send written buffer to 
done_list. 
....

I want to know how about your opinions.

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