On Thu, Jan 13, 2011 at 11:34 AM, Andy Walls <[email protected]> wrote: > Devin, > > You've seen the clock stretch with your I2C analyzer?
The Beagle I was using when I did the captures doesn't show clock stretch. My "Logic" logic analyzer does, but I wasn't using that at the time. That said, I can say with some authority that the Zilog does put the bus into a busy state after certain operations (such as setting the send bit). Devin -- Devin J. Heitmueller - Kernel Labs http://www.kernellabs.com -- To unsubscribe from this list: send the line "unsubscribe linux-media" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
