On Mar 4, 2011, at 3:32 AM, Arindam Nath wrote:
> As per Host Controller spec v3.00, we reset SDCLK before setting
> High Speed Enable, and then set it back to avoid generating clock
> gliches.
>
> Signed-off-by: Arindam Nath <arindam.n...@amd.com>
> ---
> drivers/mmc/host/sdhci.c | 25 ++++++++++++++++++++++---
> 1 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 1645687..5d3bb11 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1277,13 +1277,12 @@ static void sdhci_set_ios(struct mmc_host *mmc,
> struct mmc_ios *ios)
> else
> ctrl &= ~SDHCI_CTRL_HISPD;
>
> - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1);
> -
> if (host->version >= SDHCI_SPEC_300) {
> u16 ctrl_2;
>
> ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
> + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1);
> /*
> * We only need to set Driver Strength if the
> * preset value enable is not set.
> @@ -1294,8 +1293,28 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
> mmc_ios *ios)
> ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
>
> sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> + } else {
> + /*
> + * According to SDHC Spec v3.00, if the Preset Value
> + * Enable in the Host Control 2 register is set, we
> + * need to reset SD Clock Enable before changing High
> + * Speed Enable to avoid generating clock gliches.
> + */
> + u16 clk;
> +
> + /* Reset SD Clock Enable */
> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + clk &= ~SDHCI_CLOCK_CARD_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
> +
> + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1);
> +
> + /* Re-enable SD Clock */
> + clk |= SDHCI_CLOCK_CARD_EN;
> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Need to ensure clock is stable before using it ---- use sdhci_set_clock
> }
> - }
> + } else
> + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL1);
>
> /*
> * Some (ENE) controllers go apeshit on some ios operation,
> --
> 1.7.1
>
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