2012/9/24 Philip Rakity <prak...@marvell.com>: > > On Sep 24, 2012, at 1:15 AM, Kevin Liu <keyuan....@gmail.com> wrote: > >> From: Kevin Liu <kl...@marvell.com> >> >> Enable the quirk SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN since >> SD_CAPABILITIES_1[15:8](BASE_FREQ) can't get correct base >> clock value. It return a fixed pre-set value like 200 on >> some sdhci-pxav3 based platforms like MMP3 while return 0 >> on the other sdhci-pxav3 based platforms. >> So we enable the quirk and get the base clock via function >> get_max_clock. >> >> Signed-off-by: Kevin Liu <kl...@marvell.com> >> --- >> drivers/mmc/host/sdhci-pxav3.c | 3 ++- >> 1 files changed, 2 insertions(+), 1 deletions(-) >> >> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c >> index e918a2b..75cc79b 100644 >> --- a/drivers/mmc/host/sdhci-pxav3.c >> +++ b/drivers/mmc/host/sdhci-pxav3.c >> @@ -249,7 +249,8 @@ static int __devinit sdhci_pxav3_probe(struct >> platform_device *pdev) >> >> host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL >> | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC >> - | SDHCI_QUIRK_32BIT_ADMA_SIZE; >> + | SDHCI_QUIRK_32BIT_ADMA_SIZE >> + | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; >> >> /* enable 1/8V DDR capable */ >> host->mmc->caps |= MMC_CAP_1_8V_DDR; >> -- >> 1.7.0.4 >> > > > Kevin, > > would you mind adding: > > Reported-by: Philip Rakity <prak...@marvell.com> since I originally sent you > different code to fix this. > Sure, I will add this.
> This patch is NOT sufficient to fix the problem since the clock code was not > correct in the marvell mmp3 code. > Has someone sent upstream the patch to fix the base code in linux ? > I think mmp3 clock code has not been pushed to opensource. This patch is for the driver side. > Reviewed-by: Philip Rakity <prak...@marvell.com> -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
