With preset value enabled, SD clock should be reset before enable
both high speed and UHS-I mode. Current code enable them one by one
and do two continuous times of clock disable/enable. The operation
can be combined into once to save time and make code cleaner.

1. disable clock ->
2. enable high speed (Host Control 1 Register, 0x28<2>) ->
3. enable clock ->
4. disable clock ->
5. enable UHS-I mode (Host Control 2 Register, 0x3E<2:0>) ->
6. enable clock

This patch removed above step 3 and 4.

Signed-off-by: Kevin Liu <kl...@marvell.com>
---
 drivers/mmc/host/sdhci.c |   27 +++++++++------------------
 1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e6da79f..7784756 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1450,31 +1450,22 @@ static void sdhci_do_set_ios(struct sdhci_host *host, 
struct mmc_ios *ios)
                                ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
 
                        sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
-               } else {
-                       /*
-                        * According to SDHC Spec v3.00, if the Preset Value
-                        * Enable in the Host Control 2 register is set, we
-                        * need to reset SD Clock Enable before changing High
-                        * Speed Enable to avoid generating clock gliches.
-                        */
-
-                       /* Reset SD Clock Enable */
-                       clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-                       clk &= ~SDHCI_CLOCK_CARD_EN;
-                       sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
-
-                       sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-
-                       /* Re-enable SD Clock */
-                       sdhci_update_clock(host);
                }
 
-
                /* Reset SD Clock Enable */
                clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
                clk &= ~SDHCI_CLOCK_CARD_EN;
                sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 
+               /*
+                * According to SDHC Spec v3.00, if the Preset Value
+                * Enable in the Host Control 2 register is set, we
+                * need to reset SD Clock Enable before changing High
+                * Speed Enable to avoid generating clock gliches.
+                */
+               if (ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)
+                       sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
                if (host->ops->set_uhs_signaling)
                        host->ops->set_uhs_signaling(host, ios->timing);
                else {
-- 
1.7.9.5

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