Acked-by: Jaehoon Chung <jh80.ch...@samsung.com>
Best Regards,
Jaehoon Chung
On 03/07/2014 10:31 PM, Seungwon Jeon wrote:
> Replaced UHS_DDR50 with MMC_DDR52. And MMC_CAP_UHS_DDR50
> is removed because of non-implementation of UHS signaling.
>
> Signed-off-by: Seungwon Jeon <tgih....@samsung.com>
> Reviewed-by: Ulf Hansson <ulf.hans...@linaro.org>
> ---
> drivers/mmc/host/dw_mmc-exynos.c | 5 ++---
> drivers/mmc/host/dw_mmc.c | 2 +-
> 2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c
> b/drivers/mmc/host/dw_mmc-exynos.c
> index 3423c5e..a67e784 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -187,7 +187,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
> struct mmc_ios *ios)
> unsigned long actual;
> u8 div = priv->ciu_div + 1;
>
> - if (ios->timing == MMC_TIMING_UHS_DDR50) {
> + if (ios->timing == MMC_TIMING_MMC_DDR52) {
> mci_writel(host, CLKSEL, priv->ddr_timing);
> /* Should be double rate for DDR mode */
> if (ios->bus_width == MMC_BUS_WIDTH_8)
> @@ -386,8 +386,7 @@ static int dw_mci_exynos_execute_tuning(struct
> dw_mci_slot *slot, u32 opcode,
>
> /* Common capabilities of Exynos4/Exynos5 SoC */
> static unsigned long exynos_dwmmc_caps[4] = {
> - MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
> - MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
> + MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
> MMC_CAP_CMD23,
> MMC_CAP_CMD23,
> MMC_CAP_CMD23,
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 0c56faa..ab704d9 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -962,7 +962,7 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct
> mmc_ios *ios)
> regs = mci_readl(slot->host, UHS_REG);
>
> /* DDR mode set */
> - if (ios->timing == MMC_TIMING_UHS_DDR50)
> + if (ios->timing == MMC_TIMING_MMC_DDR52)
> regs |= ((0x1 << slot->id) << 16);
> else
> regs &= ~((0x1 << slot->id) << 16);
>
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