Am 30.09.2014 um 13:00 schrieb Ulf Hansson:
> On 30 September 2014 12:11, Oleksij Rempel <li...@rempel-privat.de> wrote:
>> Am 09.07.2014 um 14:52 schrieb Ulf Hansson:
>>> [snip]
>>>
>>>>>
>>>>> I am just a bit curious, does this controller support hardware busy
>>>>> detection on DAT1 line while waiting for command completion?
>>>>
>>>> Do you mean AU6601_REG_BUS_STATUS?
>>>> See at the beginning of patch.
>>>
>>> While reviewing the code, it seems like the controller are handling
>>> hardware busy detection on DAT1. On the other hand you don't enable
>>> MMC_CAP_WAIT_WHILE_BUSY, shouldn't you be doing that?
>>
>> Hi Ulf,
>>
>> what is better way to use sg with dma? This controller support only
>> 0x4000 alight addresses. It is possible to solve it per driver basis,
>> but i have seen already more then one driver which need it. Should it be
>> done in  mmc block code? Any other suggestions?
> 
> I don't quite follow. Does your DMA controller put constraints on
> buffer alignment/length or is it the mmc controller?

mmc controller. it can only accept addresses aligned to the PAGE_SIZE.

> I am aware of that drivers may have special treatments of buffer
> alignment/length to be able to handle some corner cases. And yes we
> don't have a common interface in the mmc core to handle that. I am not
> sure how that could be done? Do you have any suggestions?

hmm... theoretically SG allocation should always be page aligned.
Right now i found probable reason for this issue. Looks like i
misinterpreted max_segs parameter. If i use value bigger then 1, then
can get fragmented SG request. For example, by limit to blk_size=512,
block_count=8 and  max_segs > 1 request will be 4K (=page size), but the
request can be spread to different pages with offsets != the page begin.
Which is not optimal for many reasons. On other side, if max_segs=1,
then all requests will be aligned.
I don't know if it is expected behavior. If yes, then looks like some
drivers can be simplified just by setting max_segs=1.

-- 
Regards,
Oleksij

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