On 1/15/20 10:57 PM, Aneesh Kumar K.V wrote:
On 1/15/20 10:25 PM, Jeff Moyer wrote:
"Aneesh Kumar K.V" <aneesh.ku...@linux.ibm.com> writes:
Currently, kernel shows the below values
"persistence_domain":"cpu_cache"
"persistence_domain":"memory_controller"
"persistence_domain":"unknown"
This patch updates the meaning of these values such that
"cpu_cache" indicates no extra instructions is needed to ensure the
persistence
of data in the pmem media on power failure.
"memory_controller" indicates platform provided instructions need to
be issued
as per documented sequence to make sure data flushed is guaranteed to
be on pmem
media in case of system power loss.
Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.ibm.com>
---
arch/powerpc/platforms/pseries/papr_scm.c | 7 ++++++-
include/linux/libnvdimm.h | 6 +++---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c
b/arch/powerpc/platforms/pseries/papr_scm.c
index c2ef320ba1bf..26a5ef263758 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -360,8 +360,13 @@ static int papr_scm_nvdimm_init(struct
papr_scm_priv *p)
if (p->is_volatile)
p->region = nvdimm_volatile_region_create(p->bus, &ndr_desc);
- else
+ else {
+ /*
+ * We need to flush things correctly to guarantee persistance
+ */
+ set_bit(ND_REGION_PERSIST_MEMCTRL, &ndr_desc.flags);
p->region = nvdimm_pmem_region_create(p->bus, &ndr_desc);
+ }
if (!p->region) {
dev_err(dev, "Error registering region %pR from %pOF\n",
ndr_desc.res, p->dn);
Would you also update of_pmem to indicate the persistence domain,
please?
sure.
diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h
index f2a33f2e3ba8..9126737377e1 100644
--- a/include/linux/libnvdimm.h
+++ b/include/linux/libnvdimm.h
@@ -52,9 +52,9 @@ enum {
*/
ND_REGION_PERSIST_CACHE = 1,
/*
- * Platform provides mechanisms to automatically flush outstanding
- * write data from memory controler to pmem on system power loss.
- * (ADR)
+ * Platform provides instructions to flush data such that on
completion
+ * of the instructions, data flushed is guaranteed to be on pmem
even
+ * in case of a system power loss.
I find the prior description easier to understand.
I was trying to avoid the term 'automatically, 'memory controler' and
ADR. Can I update the above as
/*
* Platform provides mechanisms to flush outstanding write data
* to pmem on system power loss.
*/
Wanted to add more details. So with the above interpretation, if the
persistence_domain is found to be 'cpu_cache', application can expect a
store instruction to guarantee persistence. If it is 'none' there is no
persistence ( I am not sure how that is the difference from 'volatile'
pmem region). If it is 'memory_controller' ( I am not sure whether that
is the right term), application needs to follow the recommended
mechanism to flush write data to pmem.
-aneesh
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