On Fri, Feb 12, 2021 at 02:25:35PM -0800, Ben Widawsky wrote: > From: Dan Williams <dan.j.willi...@intel.com> > > Create the /sys/bus/cxl hierarchy to enumerate: > > * Memory Devices (per-endpoint control devices) > > * Memory Address Space Devices (platform address ranges with > interleaving, performance, and persistence attributes) > > * Memory Regions (active provisioned memory from an address space device > that is in use as System RAM or delegated to libnvdimm as Persistent > Memory regions). > > For now, only the per-endpoint control devices are registered on the > 'cxl' bus. However, going forward it will provide a mechanism to > coordinate cross-device interleave. > > Signed-off-by: Dan Williams <dan.j.willi...@intel.com> > Signed-off-by: Ben Widawsky <ben.widaw...@intel.com> > Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com> (v2)
arm:allmodconfig, i386:allyesconfig, mips:allmodconfig: drivers/cxl/mem.c:335:2: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration] 335 | writeq(cmd_reg, cxlm->mbox_regs + CXLDEV_MBOX_CMD_OFFSET); In file included from <command-line>: drivers/cxl/mem.c: In function '__cxl_mem_mbox_send_cmd': include/linux/compiler_types.h:320:38: error: call to '__compiletime_assert_266' declared with attribute error: FIELD_GET: mask is zero and many similar errors. Guenter _______________________________________________ Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org To unsubscribe send an email to linux-nvdimm-le...@lists.01.org
