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Op 6 mei 2008, om 07:38 heeft Koen Kooi het volgende geschreven:
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Op 6 mei 2008, om 01:27 heeft Woodruff, Richard het volgende
geschreven:
Hi,
Looks like a tweak from the ARM or TI tree may be needed. Builds
of recent pulls of the OMAP3 kernel show L2 cache is disabled. This
really has a huge performance impact.
I don't have time right now to suggest a patch but may look some
time this week. TI internal kernels do have it enabled.
A stop in Lauterbach and a look at the L2EN bit in AUX control
register will show it is not correct.
Enabling L2 cache was removed from proc-v7.S since was cortex
specific instead of armv7 specific
For reference:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=7092fc38ee770251aed361572bf6bed05fcf3ee2
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