When the I2C controller is initialised, software reset is performed to
the controller. I've never seen that taking more than 1 ns while the
msleep call causes excessive delays in I2C transfers.
Tested on OMAP 3.
Signed-off-by: Sakari Ailus <[EMAIL PROTECTED]>
---
drivers/i2c/busses/i2c-omap.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index b2b0e2f..b19b851 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -40,6 +40,8 @@
/* timeout waiting for the controller to respond */
#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
+/* no more busyloop in ns */
+#define OMAP_I2C_MINOR_TIMEOUT 10
#define OMAP_I2C_REV_REG 0x00
#define OMAP_I2C_IE_REG 0x04
@@ -255,6 +257,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
unsigned long internal_clk = 0;
if (!dev->rev1) {
+ int delay = 0;
+
omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
/* For some reason we need to set the EN bit before the
* reset done bit gets set. */
@@ -262,6 +266,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
OMAP_I2C_SYSS_RDONE)) {
+ if (delay < OMAP_I2C_MINOR_TIMEOUT) {
+ ndelay(1);
+ delay++;
+ continue;
+ } else if (delay == OMAP_I2C_MINOR_TIMEOUT) {
+ dev_warn(dev->dev, "minor timeout not enough");
+ delay++;
+ }
if (time_after(jiffies, timeout)) {
dev_warn(dev->dev, "timeout waiting "
"for controller reset\n");
--
1.5.0.6
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