This patch explicitly initializes McBSP Transmit Configuration
Control Register (XCCR) and Receive Configuration Control
Register (RCCR) to their reset values. Reset values are 26 ns
of DX delay and Transmit DMA disabled for XCCR register;
receive full cycle mode enabled and Receive DMA disabled for
RCCR register.
Signed-off-by: Misael Lopez Cruz <x0052...@ti.com>
---
sound/soc/omap/omap-mcbsp.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index 8485a8a..f50cbaf 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -295,6 +295,10 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai
*cpu_dai,
regs->spcr1 |= RINTM(3);
regs->rcr2 |= RFIG;
regs->xcr2 |= XFIG;
+ if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+ regs->xccr = DXENDLY(1) | XDMAEN;
+ regs->rccr = RFULL_CYCLE | RDMAEN;
+ }
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
--
1.5.4.3
--
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