[PATCH 35/55] ARM: OMAP3: PRM: remove direct register declaration macros

Tero Kristo Mon, 31 Mar 2014 08:19:32 -0700

Only a handful of these are currently used in the kernel, so cleanup.

Signed-off-by: Tero Kristo <t-kri...@ti.com>
---
 arch/arm/mach-omap2/cclock3xxx_data.c |   14 ++++++++-----
 arch/arm/mach-omap2/prm3xxx.h         |   37 ---------------------------------
 2 files changed, 9 insertions(+), 42 deletions(-)


diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c 
b/arch/arm/mach-omap2/cclock3xxx_data.c
index d5fefb9..6d7aea5 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -79,12 +79,15 @@ static const char *osc_sys_ck_parent_names[] = {
 };
 
 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
-              OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
-              OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
+              OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, OMAP3_PRM_CLKSEL_OFFSET),
+              OMAP3430_SYS_CLKIN_SEL_SHIFT, OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0,
+              NULL);
 
 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
-                  OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
-                  OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
+                  OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD,
+                                       OMAP3_PRM_CLKSRC_CTRL_OFFSET),
+                  OMAP_SYSCLKDIV_SHIFT, OMAP_SYSCLKDIV_WIDTH,
+                  CLK_DIVIDER_ONE_BASED, NULL);
 
 static struct dpll_data dpll3_dd = {
        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
@@ -2824,7 +2827,8 @@ static struct clk_hw_omap sys_clkout1_hw = {
        .hw = {
                .clk = &sys_clkout1,
        },
-       .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+       .enable_reg     = OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD,
+                                              OMAP3_PRM_CLKOUT_CTRL_OFFSET),
        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 };
 
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index c79f4c6..ffc8177 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -34,83 +34,46 @@
  */
 
 #define OMAP3_PRM_REVISION_OFFSET      0x0004
-#define OMAP3430_PRM_REVISION          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
 #define OMAP3_PRM_SYSCONFIG_OFFSET     0x0014
-#define OMAP3430_PRM_SYSCONFIG         OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
 
 #define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU     OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
 #define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU     OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
 
 
 #define OMAP3_PRM_VC_SMPS_SA_OFFSET    0x0020
-#define OMAP3430_PRM_VC_SMPS_SA                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
 #define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET        0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA    OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0024)
 #define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET        0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA    OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0028)
 #define OMAP3_PRM_VC_CMD_VAL_0_OFFSET  0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x002c)
 #define OMAP3_PRM_VC_CMD_VAL_1_OFFSET  0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0030)
 #define OMAP3_PRM_VC_CH_CONF_OFFSET    0x0034
-#define OMAP3430_PRM_VC_CH_CONF                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
 #define OMAP3_PRM_VC_I2C_CFG_OFFSET    0x0038
-#define OMAP3430_PRM_VC_I2C_CFG                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
 #define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x003c)
 #define OMAP3_PRM_RSTCTRL_OFFSET       0x0050
-#define OMAP3430_PRM_RSTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0050)
 #define OMAP3_PRM_RSTTIME_OFFSET       0x0054
-#define OMAP3430_PRM_RSTTIME           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0054)
 #define OMAP3_PRM_RSTST_OFFSET 0x0058
-#define OMAP3430_PRM_RSTST             OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0058)
 #define OMAP3_PRM_VOLTCTRL_OFFSET      0x0060
-#define OMAP3430_PRM_VOLTCTRL          OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0060)
 #define OMAP3_PRM_SRAM_PCHARGE_OFFSET  0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0064)
 #define OMAP3_PRM_CLKSRC_CTRL_OFFSET   0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0070)
 #define OMAP3_PRM_VOLTSETUP1_OFFSET    0x0090
-#define OMAP3430_PRM_VOLTSETUP1                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
 #define OMAP3_PRM_VOLTOFFSET_OFFSET    0x0094
-#define OMAP3430_PRM_VOLTOFFSET                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
 #define OMAP3_PRM_CLKSETUP_OFFSET      0x0098
-#define OMAP3430_PRM_CLKSETUP          OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x0098)
 #define OMAP3_PRM_POLCTRL_OFFSET       0x009c
-#define OMAP3430_PRM_POLCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x009c)
 #define OMAP3_PRM_VOLTSETUP2_OFFSET    0x00a0
-#define OMAP3430_PRM_VOLTSETUP2                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
 #define OMAP3_PRM_VP1_CONFIG_OFFSET    0x00b0
-#define OMAP3430_PRM_VP1_CONFIG                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
 #define OMAP3_PRM_VP1_VSTEPMIN_OFFSET  0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00b4)
 #define OMAP3_PRM_VP1_VSTEPMAX_OFFSET  0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00b8)
 #define OMAP3_PRM_VP1_VLIMITTO_OFFSET  0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00bc)
 #define OMAP3_PRM_VP1_VOLTAGE_OFFSET   0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00c0)
 #define OMAP3_PRM_VP1_STATUS_OFFSET    0x00c4
-#define OMAP3430_PRM_VP1_STATUS                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
 #define OMAP3_PRM_VP2_CONFIG_OFFSET    0x00d0
-#define OMAP3430_PRM_VP2_CONFIG                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
 #define OMAP3_PRM_VP2_VSTEPMIN_OFFSET  0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00d4)
 #define OMAP3_PRM_VP2_VSTEPMAX_OFFSET  0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00d8)
 #define OMAP3_PRM_VP2_VLIMITTO_OFFSET  0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00dc)
 #define OMAP3_PRM_VP2_VOLTAGE_OFFSET   0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 
0x00e0)
 #define OMAP3_PRM_VP2_STATUS_OFFSET    0x00e4
-#define OMAP3430_PRM_VP2_STATUS                
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
 
 #define OMAP3_PRM_CLKSEL_OFFSET        0x0040
-#define OMAP3430_PRM_CLKSEL            OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 
0x0040)
 #define OMAP3_PRM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL       OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 
0x0070)
 
 /* OMAP3 specific register offsets */
 #define OMAP3430ES2_PM_WKEN3                           0x00f0
-- 
1.7.9.5

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[PATCH 35/55] ARM: OMAP3: PRM: remove direct register declaration macros

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