On Mon, Nov 24, 2014 at 11:08:48AM -0800, Kevin Hilman wrote: > On Sat, Nov 22, 2014 at 11:47 AM, Alexander Kochetkov > <al.koc...@gmail.com> wrote: > > In a multimaster environment, after IP software reset, BB-bit value doesn't > > correspond to the current bus state. It may happen what BB-bit will be 0, > > while the bus is busy due to another I2C master activity. > > > > Any transfer started when BB=0 and bus is busy wouldn't be completed by IP > > and results in controller timeout. More over, in some cases IP could > > interrupt another master's transfer and corrupt data on wire. > > > > The commit implement method allowing to prevent IP from entering into > > "controller timeout" state and from "data corruption" state. > > > > The one drawback is the need to wait for 10ms before the first transfer. > > > > Tested on Beagleboard XM C. > > Tested on BBB and AM437x Starter Kit by Felipe Balbi. > > > > Signed-off-by: Alexander Kochetkov <al.koc...@gmail.com> > > Tested-by: Felipe Balbi <ba...@ti.com> > > Reviewed-by: Felipe Balbi <ba...@ti.com> > > This patch recently hit linux-next (as commit 903c3859f77f) and boot > breakage[1] in next-20141124 on OMAP3530 Beagle and Overo/Tobi boards > was bisected down to this commit. > > Kevin > > [1] http://status.armcloud.us/boot/?next-20141124&omap
btw, based on Kevin's boot test, only OMAP3530 is failing. -- balbi
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