OMAP5 SoC has Cortex-A15 which does not use TWD timer. It uses
ARCH_TIMER instead, clean up unwanted configuration and enable
OMAP_INTERCONNECT and OPP which is necessary for expected functionality
on the SoC.

Reported-by: Carlos Hernandez <c...@ti.com>
Reported-by: Felipe Balbi <ba...@ti.com>
Signed-off-by: Nishanth Menon <n...@ti.com>
---
 arch/arm/mach-omap2/Kconfig |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 403022a38607..b3a0dff67e3f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -44,10 +44,11 @@ config SOC_OMAP5
        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
        select HAVE_ARM_SCU if SMP
-       select HAVE_ARM_TWD if SMP
        select HAVE_ARM_ARCH_TIMER
        select ARM_ERRATA_798181 if SMP
+       select OMAP_INTERCONNECT
        select OMAP_INTERCONNECT_BARRIER
+       select PM_OPP if PM
 
 config SOC_AM33XX
        bool "TI AM33XX"
-- 
1.7.9.5

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