On 12/22/2015 05:27 PM, Tony Lindgren wrote:
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.
Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall".
Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Tero Kristo <t-kri...@ti.com>
Signed-off-by: Tony Lindgren <t...@atomide.com>
---
If no more comments, Tero can you please apply into an immutable
branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
- ti_adpll_wait_lock loops did not do the right thing
- We want to use CLK_GET_RATE_NOCACHE in ti_adpll_init_dco
I have just one comment below still, once that is addressed:
Conditionally-acked-by: Tero Kristo <t-kri...@ti.com>
Stephen / Michael, can you pick this up for next merge? I don't have
anything else coming for the window this time, and I am probably going
to be on vacation just nicely to not be able to push anything anyway.
<snip>
+
+/* Warn if clkout or clkoutx2 try to set unavailable parent */
+static int ti_adpll_clkout_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct ti_adpll_clkout_data *co = to_clkout(hw);
+ struct ti_adpll_data *d = co->adpll;
+
+ if (ti_adpll_clock_is_bypass(d) != index)
+ return -EAGAIN;
+
I think this part is still somewhat weird. You are not doing anything
useful in this function, so do you need to implement it at all? Just
returning -EINVAL always might work also. EAGAIN is wrong return value
anyway as it can pretty much never succeed.
-Tero
+ return 0;
+}
+
<snip>
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