From: "ext Ramirez Luna, Omar" <omar.rami...@ti.com>
Subject: RE: [RFC][PATCH] DSPBRIDGE: Video Playback Cache Optimization
Date: Wed, 10 Jun 2009 01:18:29 +0200
> Hi,
>
> [sending as plain text to l-o]
>
> Could you please comment on this patch.
>
> From: Sripal Bagadia <baga...@ti.com>
> Date: Tue, 9 Jun 2009 16:05:09 -0500
> Subject: [PATCH] DSPBRIDGE: Video Playback Cache Optimization
>
> Avoid get_user_pages cache flush overheads for uncached & reserved
> buffers (e.g. display & camera buffers).
Would it be possible to tell the case/path,
where no L_PTE_CACHEABLE/L_PTE_BUFFERABLE is set with VM_IO/VM_RESERVED ?
>
> Signed-off-by: Sripal Bagadia <baga...@ti.com>
> ---
> drivers/dsp/bridge/wmd/tiomap3430.c | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c
> b/drivers/dsp/bridge/wmd/tiomap3430.c
> index 7a9603d..a2f32e8 100644
> --- a/drivers/dsp/bridge/wmd/tiomap3430.c
> +++ b/drivers/dsp/bridge/wmd/tiomap3430.c
> @@ -1461,7 +1461,9 @@ static DSP_STATUS WMD_BRD_MemMap(struct WMD_DEV_CONTEXT
> *hDevContext,
> goto func_cont;
> }
>
> - if (vma->vm_flags & VM_IO) {
> + if ((vma->vm_flags & VM_IO) | ((vma->vm_flags & VM_RESERVED) &&
> + (~pgprot_val(vma->vm_page_prot) & L_PTE_CACHEABLE) &&
> + (~pgprot_val(vma->vm_page_prot) & L_PTE_BUFFERABLE))) {
> numUsrPgs = ulNumBytes / PG_SIZE_4K;
> mpuAddr = ulMpuAddr;
> DBG_Trace(DBG_LEVEL4, "WMD_BRD_MemMap:numOfActualTabEntries=%d,"
> --
> 1.6.2.4
>
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