<tero.kri...@nokia.com> writes:
>>>
>>> There was one report from a custom board when it made a
>>difference. I've not tried to double check
>>> this data. I don't have the reporters setup so there is no
>>guarantee I could reproduce anyway. In
>>> general optimization seemed to make sense.
>>
>>I second it.
>>
>>
>>Regards,
>>Girish
>>
>>
>
> Is there errata number available for this issue by the way? I could attach
> this to the patch.
>
> Anyway, I guess the optimization would look something like this:
>
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 210a806..7a98321 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -93,6 +93,8 @@ u32 voltage_off_while_idle;
> OMAP3430_ST_GPT5_MASK|OMAP3430_ST_GPT4_MASK|\
> OMAP3430_ST_GPT3_MASK|OMAP3430_ST_GPT2_MASK)
>
> +#define INTC_SYSCONFIG 0x10
> +
> struct power_state {
> struct powerdomain *pwrdm;
> u32 next_state;
> @@ -505,6 +507,12 @@ void omap_sram_idle(void)
> prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
> omap3_enable_io_chain();
> }
> + /*
> + * Disable INTC autoidle as it can cause interrupt controller
> + * to enter unknown state with right combination of sleep / wakeup
> + * transitions
> + */
> + omap_writel(0x0, OMAP34XX_IC_BASE + INTC_SYSCONFIG);
Except omap_write* functions are deprecated.
I'd rather see a call into the interrupt code. Something like
omap_intc_prepare_idle()
Also, isn't this only needed if CORE != ON?
> /*
> * On EMU/HS devices ROM code restores a SRDC value
> @@ -561,6 +569,8 @@ void omap_sram_idle(void)
> OMAP3430_GR_MOD,
> OMAP3_PRM_VOLTCTRL_OFFSET);
> }
> + /* Re-enable interrupt controller autoidle */
> + omap_writel(OMAP3430_AUTOIDLE, OMAP34XX_IC_BASE + INTC_SYSCONFIG);
and omap_intc_resume_idle()
Kevin
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