Hi, * Philip Balister <phi...@balister.org> [091027 13:41]: > I've been going round and round on this for a couple of days. I have > a logic analyzer (cheap USB, that is why come edges are not quite > synced) attached to the gpmc pins on a logicpd dev board. The read > cycle timings are what I expect. > > The write cycle seems to do one cycle OK, then thing go into the weeds. > > Here are the values I write into the registers: > > GPMC_CONFIG1 reg: 1200 > > GPMC_CONFIG2 reg: 40400 > > GPMC_CONFIG3 reg: 20201 > > GPMC_CONFIG4 reg: 4030403 > > GPMC_CONFIG5 reg: 1040505 > > GPMC_CONFIG6 reg: 4030000 > > and here is a screen shot of the logic analyzer: > > http://balister.dyndns.org:8008/~balister/gpmc-write.png
This won't help with your current problem probably.. But once you get things working, please take a look the gpmc.c. The GPMC values should be dynamically calculated depending on the L3 speed. There are several examples of that in gpmc-onenand.c and gpmc-smc91x.c. You should be able to calculate the timings needed from the external device data sheets. Also, Paul noted earlier that for some devices you also need to add up the latencies for the level shifter. Then while at it, maybe check with your logic analyzer to make sure the timings set using gpmc.c really are what we're trying them to? I don't think anybody has ever verified that. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
