* Vishwanath BS <vishwanath...@ti.com> [091204 01:20]: > From: Shweta Gulati <shweta.gul...@ti.com> > > DSP usage at VDD1 OPP1 and OPP2 with Smartreflex enabled and any MM UCs > running DSP codec was earlier restricted as DSP crashed. > The root cause is wrong DPLL1/DPLL2 Bypass clock at VDD1 OPP1 and OPP2. > The workaround is: > For DPLL2 (DSP) select CORECLK/4 as DPLL2 bypass clock for 3430. > Select CORECLK/2 as DPLL2 bypass clock for 3630. > During DPLL2 relock phase, DSP clock will be 83MHz/200MHz which is always OK > irrespective of Vdd1 voltage. > For DPLL1 (MPU), prior to any DVFS transition to OPP1, select CORECLK/4 > (CORECLK/2 for 3630) as DPLL1 bypass clock. > For other OPPs select CORECLK/2 (CORECLK/1 for 3630) as DPLL1 bypass > clock. > These configurations are typically set in bootloader. However bootloaders may > mess up configuration and kernel with this chang ensures that system is in a > known state. > > Signed-off-by: Vishwanath BS <vishwanath...@ti.com> > --- > arch/arm/mach-omap2/cm-regbits-34xx.h | 4 ++-- > arch/arm/mach-omap2/pm34xx.c | 19 +++++++++++++++++++ > arch/arm/mach-omap2/resource34xx.c | 20 ++++++++++++++++++++ > 3 files changed, 41 insertions(+), 2 deletions(-) > mode change 100644 => 100755 arch/arm/mach-omap2/cm-regbits-34xx.h > mode change 100644 => 100755 arch/arm/mach-omap2/pm34xx.c > mode change 100644 => 100755 arch/arm/mach-omap2/resource34xx.c
This mode change stuff does not look right. Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
