Scott Ellis wrote:
>
> The clock divider range check is wrong for the OMAP3.
>
> The MCSPI_CHxCONF.CLKD register field has a max value 0x0C
> not 0x0F. Reference was the OMAP3 TRM Rev. D manual.
>
> I don't know whether the old value was correct for OMAP24xxx
> boards so I put in some #ifdef stuff. Maybe someone with access
> to the OMAP24xxx manual could check if that is necessary.
>
>
> Signed-off-by: Scott Ellis <sc...@jumpnowtek.com>
I took a look at current 34xx TRM (Rev Z) and 2430 TRM
(Rev Z again). You're right in that the 3430 has a max
value of 0x0C for this field.
The 2430 TRM says 0x0F is valid for the corresponding
field there.
Not really sure what is the correct value, but at least
the documentation says you're right.
Hope this helps.
- Anand
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