> -----Original Message-----
> From: linux-omap-ow...@vger.kernel.org [mailto:linux-omap-
> ow...@vger.kernel.org] On Behalf Of Taneja, Archit
> Sent: Monday, July 19, 2010 5:26 PM
> To: tomi.valkei...@nokia.com
> Cc: linux-omap@vger.kernel.org; Janorkar, Mayuresh; Mittal, Mukund; Taneja,
> Archit
> Subject: [PATCH 5/5] OMAP: DSS2: Context Save and Restore of Video3 pipeline
> registers
>
> From: Mayuresh Janorkar <ma...@ti.com>
>
> Context Save and Restore of Video3 pipeline registers.
[Hiremath, Vaibhav] I still fill, we are un-necessary dividing the patch here.
This patch can very well be part of another patch,
[PATCH 2/5] OMAP: DSS2: Add Video 3 pipeline functionality in DISPC
In-fact, for me this should be consolidated single patch, something like,
OMAP: DSS2: Add Video-3 pipeline functionality
I don't see any reason why we are fragmenting this into multiple patches.
Thanks,
Vaibhav
>
> Signed-off-by: Mayuresh Janorkar <ma...@ti.com>
> Signed-off-by: Mukund Mittal <mmit...@ti.com>
> Signed-off-by: Archit Taneja <arc...@ti.com>
> ---
> drivers/video/omap2/dss/dispc.c | 104
> +++++++++++++++++++++++++++++++++++++++
> 1 files changed, 104 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/video/omap2/dss/dispc.c
> b/drivers/video/omap2/dss/dispc.c
> index 8cda961..5a6c10e
> --- a/drivers/video/omap2/dss/dispc.c
> +++ b/drivers/video/omap2/dss/dispc.c
> @@ -397,6 +397,58 @@ void dispc_save_context(void)
> SR(VID_FIR_COEF_V(1, 7));
>
> SR(VID_PRELOAD(1));
> +
> + /* VID3 */
> + if (cpu_is_omap44xx()) {
> + SR(VID3_WB_BA0(0));
> + SR(VID3_WB_BA1(0));
> + SR(VID3_POSITION);
> + SR(VID3_WB_SIZE(0));
> + SR(VID3_WB_ATTRIBUTES(0));
> + SR(VID3_WB_BUF_THRESHOLD(0));
> + SR(VID3_WB_BUF_SIZE_STATUS(0));
> + SR(VID3_WB_ROW_INC(0));
> + SR(VID3_WB_PIXEL_INC(0));
> + SR(VID3_WB_FIR(0));
> + SR(VID3_WB_PICTURE_SIZE(0));
> + SR(VID3_WB_ACCU0(0));
> + SR(VID3_WB_ACCU1(0));
> +
> + SR(VID3_WB_FIR_COEF_H(0, 0));
> + SR(VID3_WB_FIR_COEF_H(0, 1));
> + SR(VID3_WB_FIR_COEF_H(0, 2));
> + SR(VID3_WB_FIR_COEF_H(0, 3));
> + SR(VID3_WB_FIR_COEF_H(0, 4));
> + SR(VID3_WB_FIR_COEF_H(0, 5));
> + SR(VID3_WB_FIR_COEF_H(0, 6));
> + SR(VID3_WB_FIR_COEF_H(0, 7));
> +
> + SR(VID3_WB_FIR_COEF_HV(0, 0));
> + SR(VID3_WB_FIR_COEF_HV(0, 1));
> + SR(VID3_WB_FIR_COEF_HV(0, 2));
> + SR(VID3_WB_FIR_COEF_HV(0, 3));
> + SR(VID3_WB_FIR_COEF_HV(0, 4));
> + SR(VID3_WB_FIR_COEF_HV(0, 5));
> + SR(VID3_WB_FIR_COEF_HV(0, 6));
> + SR(VID3_WB_FIR_COEF_HV(0, 7));
> +
> + SR(VID3_WB_CONV_COEF(0, 0));
> + SR(VID3_WB_CONV_COEF(0, 1));
> + SR(VID3_WB_CONV_COEF(0, 2));
> + SR(VID3_WB_CONV_COEF(0, 3));
> + SR(VID3_WB_CONV_COEF(0, 4));
> +
> + SR(VID3_WB_FIR_COEF_V(0, 0));
> + SR(VID3_WB_FIR_COEF_V(0, 1));
> + SR(VID3_WB_FIR_COEF_V(0, 2));
> + SR(VID3_WB_FIR_COEF_V(0, 3));
> + SR(VID3_WB_FIR_COEF_V(0, 4));
> + SR(VID3_WB_FIR_COEF_V(0, 5));
> + SR(VID3_WB_FIR_COEF_V(0, 6));
> + SR(VID3_WB_FIR_COEF_V(0, 7));
> +
> + SR(VID3_PRELOAD);
> + }
> }
>
> void dispc_restore_context(void)
> @@ -553,6 +605,58 @@ void dispc_restore_context(void)
>
> RR(VID_PRELOAD(1));
>
> + /* VID3 */
> + if (cpu_is_omap44xx()) {
> + SR(VID3_WB_BA0(0));
> + SR(VID3_WB_BA1(0));
> + SR(VID3_POSITION);
> + SR(VID3_WB_SIZE(0));
> + SR(VID3_WB_ATTRIBUTES(0));
> + SR(VID3_WB_BUF_THRESHOLD(0));
> + SR(VID3_WB_BUF_SIZE_STATUS(0));
> + SR(VID3_WB_ROW_INC(0));
> + SR(VID3_WB_PIXEL_INC(0));
> + SR(VID3_WB_FIR(0));
> + SR(VID3_WB_PICTURE_SIZE(0));
> + SR(VID3_WB_ACCU0(0));
> + SR(VID3_WB_ACCU1(0));
> +
> + SR(VID3_WB_FIR_COEF_H(0, 0));
> + SR(VID3_WB_FIR_COEF_H(0, 1));
> + SR(VID3_WB_FIR_COEF_H(0, 2));
> + SR(VID3_WB_FIR_COEF_H(0, 3));
> + SR(VID3_WB_FIR_COEF_H(0, 4));
> + SR(VID3_WB_FIR_COEF_H(0, 5));
> + SR(VID3_WB_FIR_COEF_H(0, 6));
> + SR(VID3_WB_FIR_COEF_H(0, 7));
> +
> + SR(VID3_WB_FIR_COEF_HV(0, 0));
> + SR(VID3_WB_FIR_COEF_HV(0, 1));
> + SR(VID3_WB_FIR_COEF_HV(0, 2));
> + SR(VID3_WB_FIR_COEF_HV(0, 3));
> + SR(VID3_WB_FIR_COEF_HV(0, 4));
> + SR(VID3_WB_FIR_COEF_HV(0, 5));
> + SR(VID3_WB_FIR_COEF_HV(0, 6));
> + SR(VID3_WB_FIR_COEF_HV(0, 7));
> +
> + SR(VID3_WB_CONV_COEF(0, 0));
> + SR(VID3_WB_CONV_COEF(0, 1));
> + SR(VID3_WB_CONV_COEF(0, 2));
> + SR(VID3_WB_CONV_COEF(0, 3));
> + SR(VID3_WB_CONV_COEF(0, 4));
> +
> + SR(VID3_WB_FIR_COEF_V(0, 0));
> + SR(VID3_WB_FIR_COEF_V(0, 1));
> + SR(VID3_WB_FIR_COEF_V(0, 2));
> + SR(VID3_WB_FIR_COEF_V(0, 3));
> + SR(VID3_WB_FIR_COEF_V(0, 4));
> + SR(VID3_WB_FIR_COEF_V(0, 5));
> + SR(VID3_WB_FIR_COEF_V(0, 6));
> + SR(VID3_WB_FIR_COEF_V(0, 7));
> +
> + SR(VID3_PRELOAD);
> + }
> +
> /* enable last, because LCD & DIGIT enable are here */
> RR(CONTROL(0));
> if (cpu_is_omap44xx())
> --
> 1.5.4.7
>
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