On Thu, 16 Sep 2010, Rajendra Nayak wrote: > 4430 ES2 has a few new registers added and a few modified > from ES1. This patch adds all the register changes in PRM > and CM for OMAP4430 ES2. > > Signed-off-by: Rajendra Nayak <rna...@ti.com> > Signed-off-by: Benoît Cousson <b-cous...@ti.com>
Thanks, queued for 2.6.37 (with the UTF-8 fixed here; please fix this on your end) - Paul > Cc: Paul Walmsley <p...@pwsan.com> > Cc: Kevin Hilman <khil...@deeprootsystems.com> > --- > arch/arm/mach-omap2/cm44xx.h | 90 > ++++++++++++++++++++++++++++++++++++++++- > arch/arm/mach-omap2/prm44xx.h | 14 ++++--- > 2 files changed, 96 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h > index 336d948..3c35a87 100644 > --- a/arch/arm/mach-omap2/cm44xx.h > +++ b/arch/arm/mach-omap2/cm44xx.h > @@ -195,6 +195,42 @@ > #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 > #define OMAP4430_CM1_ABE_WDT3_CLKCTRL > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) > > +/* CM1.RESTORE_CM1 register offsets */ > +#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 > +#define OMAP4430_CM_CLKSEL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) > +#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 > +#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) > +#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 > +#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) > +#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c > +#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) > +#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 > +#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) > +#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 > +#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) > +#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 > +#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) > +#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c > +#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) > +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 > +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) > +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 > +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) > +#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 > +#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) > +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c > +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) > +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 > +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) > +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 > +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) > +#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 > +#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) > +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c > +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) > +#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 > +#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE > OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) > + > /* CM2 */ > > /* CM2.OCP_SOCKET_CM2 register offsets */ > @@ -252,8 +288,6 @@ > #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) > #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c > #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) > -#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 > -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) > #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 > #define OMAP4430_CM_CLKMODE_DPLL_USB > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) > #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 > @@ -296,6 +330,8 @@ > #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) > #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 > #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) > +#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 > +#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) > > /* CM2.CORE_CM2 register offsets */ > #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 > @@ -578,4 +614,54 @@ > #define OMAP4430_CM_CEFUSE_CLKSTCTRL > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) > #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 > #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) > + > +/* CM2.RESTORE_CM2 register offsets */ > +#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 > +#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) > +#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 > +#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) > +#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 > +#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) > +#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c > +#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) > +#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 > +#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) > +#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 > +#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) > +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 > +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) > +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c > +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) > +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 > +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) > +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 > +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) > +#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 > +#define OMAP4430_CM_D2D_STATICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) > +#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c > +#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) > +#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 > +#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) > +#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 > +#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) > +#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 > +#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) > +#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c > +#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) > +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 > +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) > +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 > +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) > +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 > +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) > +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c > +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) > +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 > +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) > +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 > +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) > +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 > +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) > +#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c > +#define OMAP4430_CM_SDMA_STATICDEP_RESTORE > OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) > #endif > diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h > index fe8ef26..59839db 100644 > --- a/arch/arm/mach-omap2/prm44xx.h > +++ b/arch/arm/mach-omap2/prm44xx.h > @@ -44,14 +44,12 @@ > #define OMAP4430_PRM_IRQSTATUS_TESLA > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) > #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 > #define OMAP4430_PRM_IRQENABLE_TESLA > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) > -#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 > -#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) > +#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 > +#define OMAP4430_CM_PRM_PROFILING_CLKCTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) > > /* PRM.CKGEN_PRM register offsets */ > #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 > #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) > -#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 > -#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) > #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 > #define OMAP4430_CM_L4_WKUP_CLKSEL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) > #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c > @@ -686,8 +684,8 @@ > #define OMAP4430_PRM_LDO_ABB_IVA_SETUP > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) > #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc > #define OMAP4430_PRM_LDO_ABB_IVA_CTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) > -#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 > -#define OMAP4430_PRM_LDO_BANDGAP_CTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) > +#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 > +#define OMAP4430_PRM_LDO_BANDGAP_SETUP > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) > #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 > #define OMAP4430_PRM_DEVICE_OFF_CTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) > #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 > @@ -698,6 +696,8 @@ > #define OMAP4430_PRM_PHASE2B_CNDP > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) > #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 > #define OMAP4430_PRM_MODEM_IF_CTRL > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) > +#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 > +#define OMAP4430_PRM_VC_ERRST > OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) > > /* > * PRCM_MPU > @@ -715,6 +715,8 @@ > /* PRCM_MPU.DEVICE_PRM register offsets */ > #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 > #define OMAP4430_PRCM_MPU_PRM_RSTST > OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) > +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 > +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT > OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) > > /* PRCM_MPU.CPU0 register offsets */ > #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 > -- > 1.6.0.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-omap" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > - Paul
