This patch provides a way to enable the GPMC limited addressing
mode which is needed to access nonmultiplexed devices.
Signed-off-by: Raphael Assenat <r...@8d.com>
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 130034b..521944a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -540,6 +540,15 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
break;
+ case GPMC_EN_LIMITEDADDRESS:
+ regval = gpmc_read_reg(GPMC_CONFIG);
+ if (wval)
+ regval |= GPMC_CONFIG_LIMITEDADDRESS;
+ else
+ regval &= ~GPMC_CONFIG_LIMITEDADDRESS;
+ gpmc_write_reg(GPMC_CONFIG, regval);
+ break;
+
default:
printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
err = -EINVAL;
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h
b/arch/arm/plat-omap/include/plat/gpmc.h
index 1527929..7fdbbb8 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -42,6 +42,7 @@
#define GPMC_NAND_DATA 0x0000000c
#define GPMC_ENABLE_IRQ 0x0000000d
+#define GPMC_EN_LIMITEDADDRESS 0x0000000e
/* ECC commands */
#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
@@ -75,6 +76,7 @@
#define GPMC_DEVICETYPE_NOR 0
#define GPMC_DEVICETYPE_NAND 2
+#define GPMC_CONFIG_LIMITEDADDRESS 0x00000002
#define GPMC_CONFIG_WRITEPROTECT 0x00000010
#define GPMC_STATUS_BUFF_EMPTY 0x00000001
#define WR_RD_PIN_MONITORING 0x00600000
--
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