This patch creats seperate irq and dma defination header file and updates the module base addresses required for HWMOD data.
Signed-off-by: Afzal Mohammed <af...@ti.com> Signed-off-by: Vaibhav Hiremath <hvaib...@ti.com> --- arch/arm/plat-omap/include/plat/am33xx.h | 40 ++++++++ arch/arm/plat-omap/include/plat/dma-33xx.h | 85 ++++++++++++++++ arch/arm/plat-omap/include/plat/dma.h | 1 + arch/arm/plat-omap/include/plat/irqs-33xx.h | 143 +++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/irqs.h | 1 + arch/arm/plat-omap/include/plat/serial.h | 5 + 6 files changed, 275 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-omap/include/plat/dma-33xx.h create mode 100644 arch/arm/plat-omap/include/plat/irqs-33xx.h diff --git a/arch/arm/plat-omap/include/plat/am33xx.h b/arch/arm/plat-omap/include/plat/am33xx.h index 06c19bb..1162d82 100644 --- a/arch/arm/plat-omap/include/plat/am33xx.h +++ b/arch/arm/plat-omap/include/plat/am33xx.h @@ -22,4 +22,44 @@ #define AM33XX_CTRL_BASE AM33XX_SCM_BASE #define AM33XX_PRCM_BASE 0x44E00000 +#define AM33XX_GPIO0_BASE 0x44E07000 +#define AM33XX_GPIO1_BASE 0x4804C000 +#define AM33XX_GPIO2_BASE 0x481AC000 +#define AM33XX_GPIO3_BASE 0x481AE000 + +#define AM33XX_TIMER0_BASE 0x44E05000 +#define AM33XX_TIMER1_BASE 0x44E31000 +#define AM33XX_TIMER2_BASE 0x48040000 +#define AM33XX_TIMER3_BASE 0x48042000 +#define AM33XX_TIMER4_BASE 0x48044000 +#define AM33XX_TIMER5_BASE 0x48046000 +#define AM33XX_TIMER6_BASE 0x48048000 +#define AM33XX_TIMER7_BASE 0x4804A000 + +#define AM33XX_WDT1_BASE 0x44E35000 + +#define AM33XX_TSC_BASE 0x44E0D000 +#define AM33XX_RTC_BASE 0x44E3E000 + +#define AM33XX_ASP0_BASE 0x48038000 +#define AM33XX_ASP1_BASE 0x4803C000 + +#define AM33XX_MMC0_BASE 0x48060100 +#define AM33XX_MMC1_BASE 0x481D8100 +#define AM33XX_MMC2_BASE 0x47810100 + +#define AM33XX_I2C0_BASE 0x44E0B000 +#define AM33XX_I2C1_BASE 0x4802A000 +#define AM33XX_I2C2_BASE 0x4819C000 + +#define AM33XX_SPI0_BASE 0x48030000 +#define AM33XX_SPI1_BASE 0x481A0000 + +#define AM33XX_DCAN0_BASE 0x481CC000 +#define AM33XX_DCAN1_BASE 0x481D0000 + +#define AM33XX_USBSS_BASE 0x47400000 +#define AM33XX_USB0_BASE 0x47401000 +#define AM33XX_USB1_BASE 0x47401800 + #endif /* __ASM_ARCH_AM33XX_H */ diff --git a/arch/arm/plat-omap/include/plat/dma-33xx.h b/arch/arm/plat-omap/include/plat/dma-33xx.h new file mode 100644 index 0000000..f78edb4 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/dma-33xx.h @@ -0,0 +1,85 @@ +/* + * AM33XX SDMA channel definitions + * + * This file is automatically generated from the AM33XX hardware databases. + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H +#define __ARCH_ARM_MACH_OMAP2_AM33XX_DMA_H + + +#define AM33XX_DMA_ICSS0_7 0 +#define AM33XX_DMA_ICSS0_6 1 +#define AM33XX_DMA_MMCHS1_W 2 +#define AM33XX_DMA_MMCHS1_R 3 +#define AM33XX_DMA_AESEIP36T0_CTXIN 4 +#define AM33XX_DMA_AESEIP36T0_DIN 5 +#define AM33XX_DMA_AESEIP36T0_DOUT 6 +#define AM33XX_DMA_AESEIP36T0_CTXOUT 7 +#define AM33XX_DMA_MCASP0_X 8 +#define AM33XX_DMA_MCASP0_R 9 +#define AM33XX_DMA_MCASP1_X 10 +#define AM33XX_DMA_MCASP1_R 11 +#define AM33XX_DMA_MCASP2_X 12 +#define AM33XX_DMA_MCASP2_R 13 +#define AM33XX_DMA_PWMSS0_EPWM 14 +#define AM33XX_DMA_PWMSS1_EPWM 15 +#define AM33XX_DMA_SPIOCP0_CH0W 16 +#define AM33XX_DMA_SPIOCP0_CH0R 17 +#define AM33XX_DMA_SPIOCP0_CH1W 18 +#define AM33XX_DMA_SPIOCP0_CH1R 19 +#define AM33XX_DMA_SPIOCP3_CH1W 20 +#define AM33XX_DMA_SPIOCP3_CH1R 21 +#define AM33XX_DMA_GPIO 22 +#define AM33XX_DMA_GPIO1 23 +#define AM33XX_DMA_MMCHS0_W 24 +#define AM33XX_DMA_MMCHS0_R 25 +#define AM33XX_DMA_UART0_0 26 +#define AM33XX_DMA_UART0_1 27 +#define AM33XX_DMA_UART1_0 28 +#define AM33XX_DMA_UART1_1 29 +#define AM33XX_DMA_UART2_0 30 +#define AM33XX_DMA_UART2_1 31 +#define AM33XX_DMA_DESEIP16T0_IN 32 +#define AM33XX_DMA_DESEIP16T0 33 +#define AM33XX_DMA_DESEIP16T0_OUT 34 +#define AM33XX_DMA_SHAEIP57T0_CTXIN 35 +#define AM33XX_DMA_SHAEIP57T0_DIN 36 +#define AM33XX_DMA_SHAEIP57T0_CTXOUT 37 +#define AM33XX_DMA_PWMSS0_ECAP 38 +#define AM33XX_DMA_PWMSS1_ECAP 39 +#define AM33XX_DMA_DCAN_1 40 +#define AM33XX_DMA_DCAN_2 41 +#define AM33XX_DMA_SPIOCP1_CH0W 42 +#define AM33XX_DMA_SPIOCP1_CH0R 43 +#define AM33XX_DMA_SPIOCP1_CH1W 44 +#define AM33XX_DMA_SPIOCP1_CH1R 45 +#define AM33XX_DMA_PWMSS0_EQEP 46 +#define AM33XX_DMA_DCAN_3 47 +#define AM33XX_DMA_TIMER_4 48 +#define AM33XX_DMA_TIMER_5 49 +#define AM33XX_DMA_TIMER_6 50 +#define AM33XX_DMA_TIMER_7 51 +#define AM33XX_DMA_GPM 52 +#define AM33XX_DMA_ADC0 53 +#define AM33XX_DMA_PWMSS1_EQEP 56 +#define AM33XX_DMA_ADC1 57 +#define AM33XX_DMA_MSHSI2COCP0_TX 58 +#define AM33XX_DMA_MSHSI2COCP0_RX 59 +#define AM33XX_DMA_MSHSI2COCP1_TX 60 +#define AM33XX_DMA_MSHSI2COCP1_RX 61 +#define AM33XX_DMA_PWMSS2_ECAP 62 +#define AM33XX_DMA_PWMSS2_EPW 63 + +#endif diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index dc562a5..c865dbc 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -30,6 +30,7 @@ /* Move omap4 specific defines to dma-44xx.h */ #include "dma-44xx.h" +#include "dma-33xx.h" /* DMA channels for omap1 */ #define OMAP_DMA_NO_DEVICE 0 diff --git a/arch/arm/plat-omap/include/plat/irqs-33xx.h b/arch/arm/plat-omap/include/plat/irqs-33xx.h new file mode 100644 index 0000000..3e12d83 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/irqs-33xx.h @@ -0,0 +1,143 @@ +/* + * AM33XX interrupts. + * + * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H +#define __ARCH_ARM_MACH_OMAP2_AM33XX_IRQS_H + + +#define AM33XX_IRQ_ELM 4 +#define AM33XX_IRQ_PI_NMI 7 +#define AM33XX_IRQ_CONTROL_PLATFORM 8 +#define AM33XX_IRQ_L3_FLAGMUX0 9 +#define AM33XX_IRQ_L3_FLAGMUX1 10 +#define AM33XX_IRQ_PRCM 11 +#define AM33XX_IRQ_TPCC0_INT_PO0 12 +#define AM33XX_IRQ_TPCC0_MPINT_PO 13 +#define AM33XX_IRQ_TPCC0_ERRINT_PO 14 +#define AM33XX_IRQ_WDT0 15 +#define AM33XX_IRQ_ADC_GEN 16 +#define AM33XX_IRQ_USBSS 17 +#define AM33XX_IRQ_USB0 18 +#define AM33XX_IRQ_USB1 19 +#define AM33XX_IRQ_ICSS0_0 20 +#define AM33XX_IRQ_ICSS0_1 21 +#define AM33XX_IRQ_ICSS0_2 22 +#define AM33XX_IRQ_ICSS0_3 23 +#define AM33XX_IRQ_ICSS0_4 24 +#define AM33XX_IRQ_ICSS0_5 25 +#define AM33XX_IRQ_ICSS0_6 26 +#define AM33XX_IRQ_ICSS0_7 27 +#define AM33XX_IRQ_MMCHS1 28 +#define AM33XX_IRQ_MMCHS2 29 +#define AM33XX_IRQ_MSHSI2COCP2 30 +#define AM33XX_IRQ_PWMSS0_ECAP 31 +#define AM33XX_IRQ_GPIO2_1 32 +#define AM33XX_IRQ_GPIO2_2 33 +#define AM33XX_IRQ_USB_P 34 +#define AM33XX_IRQ_PCI_SLV 35 +#define AM33XX_IRQ_LCD 36 +#define AM33XX_IRQ_THALIAIRQ 37 +#define AM33XX_IRQ_BB_2DHWA 38 +#define AM33XX_IRQ_PWMSS2_EPWM 39 +#define AM33XX_IRQ_CPSW_C0_RX 40 +#define AM33XX_IRQ_CPSW_RX 41 +#define AM33XX_IRQ_CPSW_TX 42 +#define AM33XX_IRQ_CPSW_C0 43 +#define AM33XX_IRQ_UART3 44 +#define AM33XX_IRQ_UART4 45 +#define AM33XX_IRQ_UART5 46 +#define AM33XX_IRQ_PWMSS1_ECAP 47 +#define AM33XX_IRQ_PCI0 48 +#define AM33XX_IRQ_PCI1 49 +#define AM33XX_IRQ_PCI2 50 +#define AM33XX_IRQ_PCI3 51 +#define AM33XX_IRQ_DCAN0_0 52 +#define AM33XX_IRQ_DCAN0_1 53 +#define AM33XX_IRQ_DCAN0_UERR 54 +#define AM33XX_IRQ_DCAN1_0 55 +#define AM33XX_IRQ_DCAN1_1 56 +#define AM33XX_IRQ_DCAN1_UERR 57 +#define AM33XX_IRQ_PWMSS0 58 +#define AM33XX_IRQ_PWMSS1 59 +#define AM33XX_IRQ_PWMSS2 60 +#define AM33XX_IRQ_PWMSS2_ECAP 61 +#define AM33XX_IRQ_GPIO3_1 62 +#define AM33XX_IRQ_GPIO3_2 63 +#define AM33XX_IRQ_MMCHS0 64 +#define AM33XX_IRQ_MCSPIOCP0 65 +#define AM33XX_IRQ_DMTIMER0 66 +#define AM33XX_IRQ_DMTIMER1 67 +#define AM33XX_IRQ_DMTIMER2 68 +#define AM33XX_IRQ_DMTIMER3 69 +#define AM33XX_IRQ_MSHSI2COCP0 70 +#define AM33XX_IRQ_MSHSI2COCP1 71 +#define AM33XX_IRQ_UART0 72 +#define AM33XX_IRQ_UART1 73 +#define AM33XX_IRQ_UART2 74 +#define AM33XX_IRQ_RTC_TIMER 75 +#define AM33XX_IRQ_RTC_ALARM 76 +#define AM33XX_IRQ_MAILBOX 77 +#define AM33XX_IRQ_M3_M3SP_TXEV 78 +#define AM33XX_IRQ_PWMSS0_EQEP 79 +#define AM33XX_IRQ_MCASP0_AX 80 +#define AM33XX_IRQ_MCASP0_AR 81 +#define AM33XX_IRQ_MCASP1_AX 82 +#define AM33XX_IRQ_MCASP1_AR 83 +#define AM33XX_IRQ_MCASP2_X 84 +#define AM33XX_IRQ_MCASP2_R 85 +#define AM33XX_IRQ_PWMSS0_EPWM 86 +#define AM33XX_IRQ_PWMSS1_EPWM 87 +#define AM33XX_IRQ_PWMSS1_EQEP 88 +#define AM33XX_IRQ_PWMSS2_EQEP 89 +#define AM33XX_IRQ_DMA 90 +#define AM33XX_IRQ_WDT1 91 +#define AM33XX_IRQ_DMTIMER4 92 +#define AM33XX_IRQ_DMTIMER5 93 +#define AM33XX_IRQ_DMTIMER6 94 +#define AM33XX_IRQ_DMTIMER7 95 +#define AM33XX_IRQ_GPIO0_1 96 +#define AM33XX_IRQ_GPIO0_2 97 +#define AM33XX_IRQ_GPIO1_1 98 +#define AM33XX_IRQ_GPIO1_2 99 +#define AM33XX_IRQ_GPMC0 100 +#define AM33XX_IRQ_EMI 101 +#define AM33XX_IRQ_AESEIP36t0_S 102 +#define AM33XX_IRQ_AESEIP36t0_P 103 +#define AM33XX_IRQ_AESEIP36t1_S 104 +#define AM33XX_IRQ_AESEIP36t1_P 105 +#define AM33XX_IRQ_DESEIP16t0_S 106 +#define AM33XX_IRQ_DESEIP16t0_P 107 +#define AM33XX_IRQ_SHAEIP57t0_S 108 +#define AM33XX_IRQ_SHAEIP57t0_P 109 +#define AM33XX_IRQ_PKAEIP29t0_S 110 +#define AM33XX_IRQ_RNGEIP75t0 111 +#define AM33XX_IRQ_TPTC0 112 +#define AM33XX_IRQ_TPTC1 113 +#define AM33XX_IRQ_TPTC2 114 +#define AM33XX_IRQ_TSC 115 +#define AM33XX_IRQ_SDMA0 116 +#define AM33XX_IRQ_SDMA1 117 +#define AM33XX_IRQ_SDMA2 118 +#define AM33XX_IRQ_SDMA3 119 +#define AM33XX_IRQ_SMARTREFLEX0 120 +#define AM33XX_IRQ_SMARTREFLEX1 121 +#define AM33XX_IRQ_NETRA_MMU 122 +#define AM33XX_IRQ_DMA0 123 +#define AM33XX_IRQ_DMA1 124 +#define AM33XX_IRQ_SPI1 125 +#define AM33XX_IRQ_SPI2 126 +#define AM33XX_IRQ_SPI 127 + +#endif diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index 30e1071..29b2032 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -30,6 +30,7 @@ /* All OMAP4 specific defines are moved to irqs-44xx.h */ #include "irqs-44xx.h" +#include "irqs-33xx.h" /* * IRQ numbers for interrupt handler 1 diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index e988c92..ec66b42 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h @@ -61,6 +61,11 @@ /* AM33XX serial port */ #define AM33XX_UART1_BASE 0x44E09000 +#define AM33XX_UART2_BASE 0x48022000 +#define AM33XX_UART3_BASE 0x48024000 +#define AM33XX_UART4_BASE 0x481A6000 +#define AM33XX_UART5_BASE 0x481A8000 +#define AM33XX_UART6_BASE 0x481AA000 /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
