On Fri, Jun 1, 2012 at 6:26 PM, Kevin Hilman <khil...@ti.com> wrote:
> Hi Jean,
>
> Jean Pihet <jean.pi...@newoldbits.com> writes:
>
>> The C1 state latency can be improved by optimizing the cpuidle low
>> level code.
>>
>> The first patch is a precaution fix for patch 2.
>> Patches 2 & 3 are optimization changes.
>>
>> Rebased on top of the for_3.6/pm/performance branch of
>> khilman's tree [1].
>>
>> Tested on Beagleboard using a DMA-enabled copy from NAND flash
>> to /dev/null.
>
> Thanks for following this through.
>
> Adding this series to my for_3.6/pm/performance branch.
Great!

>
> Also FYI, combining your series with the various fixes for CORE
> retention, I'm seeing CORE hit retention in idle just fine on 3430/n900
> and 3530/Overo.
Nice, thx for testing!

>
> Thanks!
>
> Kevin

Regards,
Jean
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