On Tue, Aug 21, 2012 at 4:14 PM, Benoit Cousson <b-cous...@ti.com> wrote: > Hi Santosh, >
[...] >>>> From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001 >>>> From: Santosh Shilimkar <santosh.shilim...@ti.com> >>>> Date: Wed, 4 Jul 2012 17:57:34 +0530 >>>> Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2 Cache Controller in Device Tree >>>> >>>> This provides PL310 Level 2 Cache Controller Device Tree >>>> support for OMAP4 based devices. >>>> >>>> Cc: Benoit Cousson <b-cous...@ti.com> >>>> Signed-off-by: Santosh Shilimkar <santosh.shilim...@ti.com> >>> >>> nice work :-) >>> >>> FWIW this looks good to me: >>> >>> Acked-by: Felipe Balbi <ba...@ti.com> >>> >> Thanks. >> >>> just one thing, will a similar patch for omap3 be sent ? >>> >> OMAP3 has an integrated L2 cache controller so there >> won't any additional DT node for L2. >> >> OMAP3 CPU DT node can be updated with l1/l2 cache >> size etc related information though. > > That's not needed if the information is available from the HW. > DT is only there to provide information that cannot be extracted from HW. > Good to know. > If CP15 registers already contains the details about caches, then there > is no need to add them in the DT file. > True. In that case as you said, there is no need to add that information in DT. Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
