On 30/12/14 13:08, Harald Servat wrote:
Dear list,
I'd like to use PEBS to sample only misses at LLC on my Intel(R)
Core(TM) i7-2760QM CPU.
I've been digging into section 18.4.4 of the Intel® 64 and IA-32
Architectures Developer's Manual: Vol. 3B and I've found that
MEM_LOAD_RETIRED does not include LLC_MISSES in that event. However, in
Table 19-13 (Section 19.6) the LLC_MISSES can be reported by setting
umask 0x10. Since I'm interested on this particular counter, I guess
that I cannot use perf mem command and I've have to stick with perf, am
I right?
In order to test this, I've modified the stream benchmark so that the
accesses are random in each of the four kernels (copy, scale, add and
triad) in order to reduce the spatial&temporal localities.
So if I run
# Capture MEM_LOAD_RETIRED.L2_HIT
perf record -c 1 -e r02cb ./stream.rand
The number of captured samples is about 2M.
However, if I run
# Capture MEM_LOAD_RETIRED.L3_MISS
perf record -c 1 -e r10cb ./stream.rand
then I get 0 samples. Is that a demonstration that it's impossible to
capture precise misses at L3? If so, is there any alternative to do
that? Could I use the latency to bring the data from the memory
hierarchy instead?
Thank you very much, and happy new year!
Any thoughts on this?
Thank you very much.
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