On Mon, Oct 19, 2015 at 09:28:43AM +0000, Vineet Gupta wrote: > On Monday 19 October 2015 11:20 AM, Andi Kleen wrote: > > Vineet Gupta <[email protected]> writes: > >> But this user space - so IMHO UP/SMP doesn't matter and we can't simulate > >> them in > >> C just by itself. > > It matters when you access the perf ring buffer which is updated by kernel. > > That's part of the problem. The issue is with atomic_* APIs proliferation in > perf > user space code which assumes native atomix r-m-w support which is not always > true. So I think we still need a feature detection mechanism and if absent > leave > the ball in arch court by calling arch_atomic_* which can use creative or half > working measures so perf will work to some extent atleast and not bomb > outright. > > Also can u please elaborate a bit on "simulate them in C" - u mean just simple > unprotected LD, OP, ST or do u fancy usage of futex etc?
Doesn't ARMv5 have a cmpxchg syscall to deal with this? It does an IRQ-disabled load-op-store sequence. -- To unsubscribe from this list: send the line "unsubscribe linux-perf-users" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
