2014-01-31 23:23 GMT+08:00 Arnd Bergmann <[email protected]>:
> On Friday 31 January 2014, Barry Song wrote:
>> >
>> > Is SRC_OSC_RATE the rate of spwm->clk? If so, it would be nice to just call
>> > clk_get_rate() here, in case you ever have a chip with a different rate.
>> >
>>
>> SRC_OSC_RATE is the fixed frequency of crystal oscillator, but
>> spwm->clk comes from the IO bus. the design is a little strange, pwm
>> channels don't use the clock of PWM controller to generate
>> period/duty, but use other sources.
>
> How about modeling that other source as a fixed-rate clock in DT
> then?
sirfsoc clock drivers have a clock node for OSC whose index is "1".
do you think the following is the right way to handle?
in dts, put both pwm controller clock and OSC
672 pwm: pwm@b0130000 {
673 compatible = "sirf,prima2-pwm";
674 #pwm-cells = <2>;
675 reg = <0xb0130000 0x10000>;
676 clocks = <&clks 21>, <&clks 1>;
677 clock-names = "pwmc", "osc";
678 };
and in pwm-sirf.c driver, use
clk = clk_get(dev, "osc");
clk_get_rate(clk);
to get the rate in probe()?
>
> Arnd
-barry
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