[[EMAIL PROTECTED]] > I'm in the same boat. How do you enable IO-APIC support in the > kernel? CONFIG_SMP implies it, and recent 2.3.x (may have been backported) will allow a UP kernel to use IO-APIC (Ingo's work) although I haven't seen a machine (personally) where that's helpful :) > What is MTRR and how is it enabled? CONFIG_MTRR=y Snipped from Documentation/Configure.help: MTRR control and configuration CONFIG_MTRR On Intel P6 family processors (Pentium Pro, Pentium II and later) the Memory Type Range Registers (MTRRs) may be used to control processor access to memory ranges. This is most useful when you have a video (VGA) card on a PCI or AGP bus. Enabling write-combining allows bus write transfers to be combined into a larger transfer before bursting over the PCI/AGP bus. This can increase performance of image write operations 2.5 times or more. This option creates a /proc/mtrr file which may be used to manipulate your MTRRs. Typically the X server should use this. This should have a reasonably generic interface so that similar control registers on other processors can be easily supported. The Cyrix 6x86, 6x86MX and M II processors have Address Range Registers (ARRs) which provide a similar functionality to MTRRs. For these, the ARRs are used to emulate the MTRRs, which means that it makes sense to say Y here for these processors as well. The AMD K6-2 (stepping 8 and above) and K6-3 processors have two MTRRs. The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. All of these processors are supported by this code. The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. These are supported. Saying Y here also fixes a problem with buggy SMP BIOSes which only set the MTRRs for the boot CPU and not the secondary CPUs. This can lead to all sorts of problems. You can safely say Y even if your machine doesn't have MTRRs, you'll just add about 9K to your kernel. See Documentation/mtrr.txt for more information. James Manning
