On Mon, Oct 26, 2015 at 10:28:45AM -0400, ira.we...@intel.com wrote:
> From: Mike Marciniszyn <mike.marcinis...@intel.com>
> 
> The workqueue is currently single threaded per port which for a small number 
> of
> SDMA engines is ok.
> 
> For hfi1, the there are up to 16 SDMA engines that can be fed descriptors in
> parallel.
> 
> This patch:
> - Converts to use alloc_workqueue
> - Changes the workqueue limit from 1 to num_sdma
> - Makes the queue WQ_CPU_INTENSIVE and WQ_HIGHPRI
> - The sdma_engine now has a cpu that is initialized
>   as the MSI-X vectors are setup
> - Adjusts the post send logic to call a new scheduler
>   that doesn't get the s_lock
> - The new and old workqueue schedule now pass a
>   cpu
> - post send now uses the new scheduler
> - RC/UC QPs now pre-compute the sc, sde
> - The sde wq is eliminated since the new hfi1_wq is
>   multi-threaded

When you have to start enumerating all of the different things that your
patch does, that's a huge hint that you need to break it up into smaller
pieces.

Please break this up, it's not acceptable as-is.

thanks,

greg k-h
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