From: Magnus Damm <damm+rene...@opensource.se>

Deprecate "renesas,channels-mask" and update the r8a7790 CMT example.

Signed-off-by: Magnus Damm <damm+rene...@opensource.se>
Acked-by: Geert Uytterhoeven <geert+rene...@glider.be>
Acked-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Acked-by: Rob Herring <r...@kernel.org>
---

 Changes since V2:
 - Added Acked-by from Rob
 - Removed Tested-by tag from DT binding patch - duh!

 Changes since V1:
 - Added Acked-by and Tested-by from Geert
 - Added Acked-by from Laurent

 Documentation/devicetree/bindings/timer/renesas,cmt.txt |   24 ++++++++++-----
 1 file changed, 17 insertions(+), 7 deletions(-)

--- 0009/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ work/Documentation/devicetree/bindings/timer/renesas,cmt.txt        
2015-09-17 17:39:47.080513000 +0900
@@ -60,21 +60,31 @@ Required Properties:
     in clock-names.
   - clock-names: must contain "fck" for the functional clock.
 
-  - renesas,channels-mask: bitmask of the available channels.
+  - renesas,channels-mask: <deprecated>, information kept in device driver.
 
 
-Example: R8A7790 (R-Car H2) CMT0 node
-
-       CMT0 on R8A7790 implements hardware channels 5 and 6 only and names
-       them channels 0 and 1 in the documentation.
+Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes
 
        cmt0: timer@ffca0000 {
-               compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
+               compatible = "renesas,cmt0-r8a7790", "renesas,cmt0-rcar-gen2";
                reg = <0 0xffca0000 0 0x1004>;
                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
                             <0 142 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
                clock-names = "fck";
+       };
 
-               renesas,channels-mask = <0x60>;
+       cmt1: timer@e6130000 {
+               compatible = "renesas,cmt1-r8a7790", "renesas,cmt1-rcar-gen2";
+               reg = <0 0xe6130000 0 0x1004>;
+               interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 121 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 122 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 123 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 124 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 125 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 126 IRQ_TYPE_LEVEL_HIGH>,
+                            <0 127 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
+               clock-names = "fck";
        };

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