Add the (previously omitted) SCIF0/3 pin data to the Blanche board's
device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>

---
Changes in version 2:
- added Geert's tag.

 arch/arm/boot/dts/r8a7792-blanche.dts |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7792-blanche.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7792-blanche.dts
+++ renesas/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -57,10 +57,28 @@
        clock-frequency = <20000000>;
 };
 
+&pfc {
+       scif0_pins: scif0 {
+               groups = "scif0_data";
+               function = "scif0";
+       };
+
+       scif3_pins: scif3 {
+               groups = "scif3_data";
+               function = "scif3";
+       };
+};
+
 &scif0 {
+       pinctrl-0 = <&scif0_pins>;
+       pinctrl-names = "default";
+
        status = "okay";
 };
 
 &scif3 {
+       pinctrl-0 = <&scif3_pins>;
+       pinctrl-names = "default";
+
        status = "okay";
 };

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