On Fri, Sep 2, 2016 at 4:32 AM, Chris Brandt <chris.bra...@renesas.com> wrote:
> Check the MD_CLK pin to determine the current clock mode in order to set
> the pll clock parent correctly.
>
> Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
> ---
> V4:
> * added static and __init to rz_cpg_read_mode_pins
> * set cpg_mode during declaration
> v3:
> * move reading GPIO port into separate function
> v2:
> * Switched to reading MD_CLK pin to determine mode
Thanks for the update, will queue in clk-renesas-for-v4.X...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
