[PATCH] clk: renesas: r8a7795: Fix HDMI parent clock

[Simon Horman]

From: Takeshi Kihara <takeshi.kihara...@renesas.com>

Correct HDMI parent clock so that the rate of the
HDMI clock is 1/4 rather than 1/2 of the rate of PLL1
as per the v0.52 (Jun, 15) manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
 drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index f255e451e8ca..eec42c249e3a 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -97,7 +97,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] 
__initconst = {
        DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
 
        DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
-       DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
+       DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
        DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
        DEF_DIV6P1("csi0",      R8A7795_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 
-- 
2.7.0.rc3.207.g0ac5344