Add the (previously omitted) Ether/PHY pin data to the SK-RZG1M board's
device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>

---
 arch/arm/boot/dts/r8a7743-sk-rzg1m.dts |   13 +++++++++++++
 1 file changed, 13 insertions(+)

Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -44,6 +44,16 @@
                groups = "scif0_data";
                function = "scif0";
        };
+
+       ether_pins: ether {
+               groups = "eth_link", "eth_mdio", "eth_rmii";
+               function = "eth";
+       };
+
+       phy1_pins: phy1 {
+               groups = "intc_irq0";
+               function = "intc";
+       };
 };
 
 &scif0 {
@@ -54,6 +64,9 @@
 };
 
 &ether {
+       pinctrl-0 = <&ether_pins &phy1_pins>;
+       pinctrl-names = "default";
+
        phy-handle = <&phy1>;
        renesas,ether-link-active-low;
        status = "okay";

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