Hello!
On 01/16/2018 05:39 PM, Yoshihiro Kaneko wrote:
From: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
Because power of Salvator-X board is cut off in suspend,
it needs to reset SATA PHY state in resume.
Otherwise, SATA partition could not be accessed anymore.
Signed-off-by: Khiem Nguyen <khiem.nguyen...@rvc.renesas.com>
Signed-off-by: Hien Dang <hien.dang...@rvc.renesas.com>
[reinit phy in sata_rcar_resume() function on R-Car Gen3 only]
[fixed the prefix for the subject]
Signed-off-by: Yoshihiro Kaneko <ykaneko0...@gmail.com>
---
This patch is based on the for-next branch of libata tree.
v2 [Yoshihiro Kaneko]
* reinit phy on R-Car Gen3 only as suggested by Geert Uytterhoeven
* use "sata_rcar" prefix for the subject as suggested by Sergei Shtylyov
drivers/ata/sata_rcar.c | 38 ++++++++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 80ee2f2..4adc0d6 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
[...]
@@ -977,11 +979,43 @@ static int sata_rcar_resume(struct device *dev)
struct sata_rcar_priv *priv = host->private_data;
void __iomem *base = priv->base;
int ret;
+ u32 val;
ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
+ /* reinit phy on R-Car Gen3 only */
+ switch (priv->type) {
+ case RCAR_GEN1_SATA:
+ case RCAR_GEN2_SATA:
+ case RCAR_R8A7790_ES1_SATA:
+ break;
+ case RCAR_GEN3_SATA:
+ sata_rcar_gen2_phy_init(priv);
+ break;
+ default:
+ dev_warn(host->dev, "SATA phy is not initialized\n");
+ break;
+ }
+
+ /* SATA-IP reset state */
+ val = ioread32(base + ATAPI_CONTROL1_REG);
+ val |= ATAPI_CONTROL1_RESET;
+ iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+ /* ISM mode, PRD mode, DTEND flag at bit 0 */
+ val = ioread32(base + ATAPI_CONTROL1_REG);
+ val |= ATAPI_CONTROL1_ISM;
+ val |= ATAPI_CONTROL1_DESE;
+ val |= ATAPI_CONTROL1_DTA32M;
+ iowrite32(val, base + ATAPI_CONTROL1_REG);
+
+ /* Release the SATA-IP from the reset state */
+ val = ioread32(base + ATAPI_CONTROL1_REG);
+ val &= ~ATAPI_CONTROL1_RESET;
+ iowrite32(val, base + ATAPI_CONTROL1_REG);
+
As it stands, we could surely do the same with a much shorter code:
if (priv->type == RCAR_GEN3_SATA) {
sata_rcar_init_controller(host);
} else {
/* ack and mask */
iowrite32(0, base + SATAINTSTAT_REG);
iowrite32(0x7ff, base + SATAINTMASK_REG);
}
But do we really need this reset/init sequence on gen1/2 chips?
MBR, Sergei
