Hello Nguyen An,
Thank you for the patch.
On Friday, 24 August 2018 07:52:29 EEST Nguyen An Hoan wrote:
> From: Hoan Nguyen An <na-h...@jinso.co.jp>
Here too a commit message would be nice.
> Signed-off-by: Hoan Nguyen An <na-h...@jinso.co.jp>
> ---
> drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 312f9fe..d0847dc 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[]
> __initconst = { };
>
> static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> + DEF_MOD("fdp0", 119, R8A77965_CLK_S0D1),
I haven't found information in the datasheet to confirm whether the parent
clock is correct. As it doesn't matter too much given that the parent clock
doesn't need to be controlled, and the FDP driver doesn't care about the clock
frequency, we can start with this without any problem.
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
> DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
> DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
--
Regards,
Laurent Pinchart
