Hi Geert, On Wednesday, September 26, 2018, Geert Uytterhoeven wrote: > > +/* The clock dividers in the table vary based on DT and register > settings */ > > +static void r7s9210_update_clk_table(struct clk *extal_clk, void > __iomem *base) > > Can be __init. > > Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be> > i.e. will queue in clk-renesas-for-v4.20, with the above fixed.
OK, thank you! Chris
