Dear Geert-san, Wolfram-san
I am very sorry for not being re-test for this patch v1 with H3ES1.*.
Although I tested with M3-N, M3W H3ES2.0 and did not test
with H3ES1.1. I discarded v1 and updated v2.
Thank you! Hoan.
On 2018/10/25 11:13, Nguyen An Hoan wrote:
From: Hoan Nguyen An <na-h...@jinso.co.jp>
Fix setting value for IRQCTL register. We are setting the last 6 bits
of (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according
to new Hardware manual values 1 are "setting prohibited" for Gen3!
Signed-off-by: Hoan Nguyen An <na-h...@jinso.co.jp>
---
drivers/thermal/rcar_gen3_thermal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/thermal/rcar_gen3_thermal.c
b/drivers/thermal/rcar_gen3_thermal.c
index 7aed533..fde3fd8 100644
--- a/drivers/thermal/rcar_gen3_thermal.c
+++ b/drivers/thermal/rcar_gen3_thermal.c
@@ -306,7 +306,7 @@ static void rcar_gen3_thermal_init(struct
rcar_gen3_thermal_tsc *tsc)
usleep_range(1000, 2000);
- rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
+ rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);
