From: Niklas Söderlund <niklas.soderlund+rene...@ragnatech.se>
Hi Geert,
This is the result of the SDHI hackathon for a possible solution to the
clock issue on early ES versions. It is based on the Gen2 solution where
a row of the possible clock settings are ignored on the effected SoC+ES
versions. The first row is not effected when reading settings left by
the bootloader, only when the setting the clock.
This is tested on H3 (ES1.0, ES2.0), M3-W (ES1.0) and M3-N together with
patches to enable HS400 with great results. No regressions found for
eMMC HS200/HS400 modes nor for SDR{25,50,104} on any of the SoCs.
Patch 1/2 adds documentation on which settings is used while 2/2 is the
real change where the quirk is implemented.
Niklas Söderlund (2):
clk: renesas: rcar-gen3: add documentation for SD clocks
clk: renesas: rcar-gen3: add HS400 quirk for SD clock
drivers/clk/renesas/rcar-gen3-cpg.c | 38 ++++++++++++++++++++---------
1 file changed, 27 insertions(+), 11 deletions(-)
--
2.19.1
