Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: linux-renesas-soc-ow...@vger.kernel.org <linux-renesas-soc-
> ow...@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 30 November 2018 08:49
> To: Biju Das <biju....@bp.renesas.com>
> Cc: Rob Herring <robh...@kernel.org>; Mark Rutland
> <mark.rutl...@arm.com>; Simon Horman <ho...@verge.net.au>; Magnus
> Damm <magnus.d...@gmail.com>; Linux-Renesas <linux-renesas-
> s...@vger.kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE
> TREE BINDINGS <devicet...@vger.kernel.org>; Geert Uytterhoeven
> <geert+rene...@glider.be>; Chris Paterson
> <chris.paters...@renesas.com>; Fabrizio Castro
> <fabrizio.cas...@bp.renesas.com>
> Subject: Re: [PATCH 2/7] ARM: dts: r8a7744: Initial SoC device tree
>
> Hi Biju,
>
> On Thu, Nov 22, 2018 at 10:23 AM Biju Das <biju....@bp.renesas.com>
> wrote:
> > Basic support for the RZ/G1N (R8A7744) SoC. Added placeholders to
> > avoid compilation error with the common platform code.
> >
> > Signed-off-by: Biju Das <biju....@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7744.dtsi
>
> > + soc {
>
> > + pfc: pin-controller@e6060000 {
> > + compatible = "renesas,pfc-r8a7744";
> > + reg = <0 0xe6060000 0 0x164>;
>
> Given the datasheet mentions (reserved) registers up to offset 0x24c, you
> may want to use 0x250 for the register block length.
>
Ok will send V2 for this.
I was in confusion to set the size as 0x164 or 0x250, since the Data sheet
mention that setting prohibited for 0x240-0x24c and is reserved.
> Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End,
Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered
No. 04586709.
