* According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
August 24, 2018, the TX clock internal delay mode isn't supported
on R-Car E3 (r8a77990) and D3 (r8a77995).
* TX clock internal delay mode is required for reliable 1Gbps communication
using the KSZ9031RNX phy present on the Ebisu and Draak boards.
Thus, the E3 based Ebisu and D3 based Draak boards can not reliably
use 1Gbps and the speed should be limited to 100Mbps.
Based on work by Kazuya Mizuguchi.
Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
---
Based on renesas-devel-2019-07-12-v5.2
v2:
* Add comment to dts as suggested by Wolfram Sang
* Correct changelog as suggested by Kieran Bingham
v1 (repost):
In earlier review Andrew Lunn suggested that we may be able to take a
different approach to this problem by using delays provided by the
KSZ9031RNX PHY. In particular MMD address 2h, Register 8h -
RGMII Clock Pad Skew.
I have consulted with Renesas regarding this suggestion, however,
unfortunately it appears that the delays provided by this solution
would be insufficient to allow for reliable 1Gbps communication.
At this point I believe the safest option is to apply this patch.
---
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 8 ++++++++
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 83fc13ac3fa1..62203c0fc70d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -271,6 +271,14 @@
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ /*
+ * TX clock internal delay mode is required for reliable
+ * 1Gbps communication using the KSZ9031RNX phy present on
+ * the Ebisu board, however, TX clock internal delay mode
+ * isn't supported on r8a77990. Thus, limit speed to
+ * 100Mbps for reliable communication.
+ */
+ max-speed = <100>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 0711170b26b1..4b651548b82b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -175,6 +175,14 @@
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ /*
+ * TX clock internal delay mode is required for reliable
+ * 1Gbps communication using the KSZ9031RNX phy present on
+ * the Draak board, however, TX clock internal delay mode
+ * isn't supported on r8a77995. Thus, limit speed to
+ * 100Mbps for reliable communication.
+ */
+ max-speed = <100>;
};
};
--
2.11.0
