Hi Shimoda-san,
On Wed, Oct 9, 2019 at 1:05 PM Yoshihiro Shimoda
<[email protected]> wrote:
> According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register
> should be written to 0 before enabling PCIETCTLR.CFINIT because
> the bit 0 is set to 1 on reset. To avoid unexpected behaviors from
> this incorrect setting, this patch fixes it.
>
> Fixes: c25da4778803 ("PCI: rcar: Add Renesas R-Car PCIe driver")
> Cc: <[email protected]> # v3.16+
> Signed-off-by: Yoshihiro Shimoda <[email protected]>
> Reviewed-by: Sergei Shtylyov <[email protected]>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> ---
> Changes from v2:
> - Change the subject.
> - Fix commit log again.
> - Add the register setting into the initialization, instead of speedup.
> - Change commit hash/target version on Fixes and Cc stable tags.
> - Add Geert-san's Reviewed-by.
> https://patchwork.kernel.org/patch/11180429/
Thanks for the update!
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -93,6 +93,7 @@
> #define LINK_SPEED_2_5GTS (1 << 16)
> #define LINK_SPEED_5_0GTS (2 << 16)
> #define MACCTLR 0x011058
> +#define MACCTLR_RESERVED BIT(0)
> #define SPEED_CHANGE BIT(24)
> #define SCRAMBLE_DISABLE BIT(27)
> #define PMSR 0x01105c
> @@ -615,6 +616,8 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
> if (IS_ENABLED(CONFIG_PCI_MSI))
> rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
>
> + rcar_rmw32(pcie, MACCTLR, MACCTLR_RESERVED, 0);
> +
> /* Finish initialization - establish a PCI Express link */
> rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
I guess the same should be added to rcar_pcie_resume_noirq(),
as s2ram on R-Car Gen3 powers down the SoC?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
